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general description the max4731/max4732/max4733 low-voltage, dual, single-pole/single-throw (spst) analog switches oper- ate from a single +2v to +11v supply and handle rail- to-rail analog signals. these switches exhibit low leakage current (0.1na) and consume less than 0.5nw (typ) of quiescent power, making them ideal for battery- powered applications. when powered from a +3v supply, these switches fea- ture 50 ? (max) on-resistance (r on ) with 3.5 ? (max) matching between channels, and 9 ? (max) flatness over the specified signal range. the max4731 has two normally open (no) switches, the max4732 has two normally closed (nc) switches, and the max4733 has one no and one nc switch. the max4731/max4732/max4733 are available in 9-bump chip-scale packages (ucsp), along with 8-pin tdfn and 8-pin ?ax packages. the tiny ucsp occupies a 1.52mm ? 1.52mm area and significantly reduces the required pc board area. applications battery-powered systems audio/video-signal routing low-voltage data-acquisition systems cell phones communications circuits pdas features 1.52mm ? 1.52mm ucsp package guaranteed on-resistance (r on ) 25 ? (max) at +5v 50 ? (max) at +3v on-resistance matching 3 ? (max) at +5v 3.5 ? (max) at +3v guaranteed < 0.1na leakage current at t a = +25? single-supply operation from +2.0v to +11v ttl/cmos-logic compatible -108db crosstalk (1mhz) -72db off-isolation (1mhz) low power consumption: 0.5nw (typ) rail-to-rail signal handling max4731/max4732/max4733 50 ?, dual spst analog switches in ucsp ________________________________________________________________ maxim integrated products 1 ordering information 19-2645; rev 2 12/06 for pricing, delivery, and ordering information, please contact maxim/dallas direct! at 1-888-629-4642, or visit maxim? website at www.maxim-ic.com. part temp range pin/bump- package top mark max4731 eua -40 c to +85 c 8 max MAX4731ETA -40 c to +85 c 8 tdfn-ep** alg max4731ebl- -40 c to +85 c 9 ucsp-9 abv max4732 eua -40 c to +85 c 8 max max4732eta -40 c to +85 c 8 tdfn-ep** alh max4732ebl- -40 c to +85 c 9 ucsp-9 abt max4733 eua -40 c to +85 c 8 max max4733eta -40 c to +85 c 8 tdfn-ep** ali max4733ebl- -40 c to +85 c 9 ucsp-9 abs no2 v+ gnd in2 in1 no1 com1 com2 top view (bumps on bottom) ucsp max4731 a1 b1 c1 c2 c3 b3 a3 a2 max4732 nc2 v+ gnd in2 in1 nc1 com1 com2 ucsp a1 b1 c1 c2 c3 b3 a3 a2 in_ 0 1 no_ max4731 off on switches shown for logic "0" input in_ 0 1 nc_ max4732 on off switches shown for logic "0" input com1 gnd no1 tdfn max4731 com2 no2 in1 1 2 in2 3 4 8 7 6 5 com1 gnd nc1 tdfn max4732 in1 com2 v+ 1 2 in2 3 4 8 7 6 5 top view (bumps on bottom) v+ nc2 pin configurations/functional diagrams/truth tables ucsp is a trademark of maxim integrated products, inc. ?ax is a registered trademark of maxim integrated products, inc. pin configurations/functional diagrams/truth tables continued at end of data sheet. * future product?ontact factory for availability. ** ep = exposed pad.
max4731/max4732/max4733 50 ?, dual spst analog switches in ucsp 2 _______________________________________________________________________________________ absolute maximum ratings electrical characteristics single +3v supply (v+ = +3v 10%, v ih = +2.0v, v il = +0.8v, t a = t min to t max , unless otherwise noted. typical values are at v+ = +3v, t a = +25 c.) (notes 3, 4) stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. (all voltages referenced to gnd.) v+ ...........................................................................-0.3v to +12v in_, com_, no_, nc_ (note 1)....................-0.3v to (v+ + 0.3v) continuous current (any pin) ...........................................10ma peak current (any pin, pulsed at 1ms, 10% duty cycle) ...20ma continuous power dissipation (t a = +70 c) 8-pin max (derate 4.5mw/ c above +70 c) .............362mw 8-pin tdfn (derate 24.4mw/ c above +70 c) .........1951mw 9-bump ucsp (derate 4.7mw/ c above +70 c).........379mw operating temperature range ...........................-40 c to +85 c storage temperature range .............................-65 c to +150 c maximum junction temperature .....................................+150 c lead temperature (soldering, 10s) .................................+300 c bump temperature (soldering, note 2) infrared (15s) ...............................................................+220 c vapor phase (60s) .......................................................+215 c note 1: signals on in_, no_, nc_, or com_ exceeding v+ or gnd are clamped by internal diodes. limit forward-diode current to maximum current rating. note 2: this device is constructed using a unique set of packaging techniques that impose a limit on the thermal profile the device can be exposed to during board level solder attach and rework. this limit permits only the use of the solder profiles recom- mended in the industry-standard specification, jedec 020a, paragraph 7.6, table 3 for ir/vpr and convection reflow. pre- heating is required. hand or wave soldering is not allowed. parameter symbol conditions t a min typ max units analog switch analog signal range v com_ , v no_ , v nc_ 0v+v +25 c 19 50 on-resistance r on v+ = +2.7v, i com_ = 5ma; v no_ or v nc_ = +1.5v t min to t max 60 ? c 0.8 3.5 on-resistance matching between channels (notes 5, 6) ? r on v+ = +2.7v, i com_ = 5ma; v no_ or v nc_ = +1.5v t min to t max 4.5 ? c 2.3 9 on-resistance flatness (note 7) r flat ( on ) v+ = +2.7v, i com_ = 5ma; v no_ or v nc_ = +1v, +1.5v, +2v t min to t max 11 ? c -0.1 +0.1 no_ or nc_ off-leakage current (note 8) i no_ ( off ) i nc_ ( off ) v+ = +3.6v, v com_ = +0.3v, +3v; v no_ or v nc_ = +3v, +0.3v t min to t max -2 +2 na +25 c -0.1 +0.1 com_ off-leakage current (note 8) i com_ ( off ) v+ = +3.6v, v com_ = +0.3v, +3v; v no_ or v nc_ = +3v, +0.3v t min to t max -2 +2 na +25 c -0.2 +0.2 com_ on-leakage current (note 8) i com_ ( on ) v+ = +3.6v, v com_ = +0.3v, +3.0v; v no_ or v nc_ = +0.3v, +3v, or floating t min to t max -4 +4 na
max4731/max4732/max4733 50 ?, dual spst analog switches in ucsp _______________________________________________________________________________________ 3 electrical characteristics single +3v supply (continued) (v+ = +3v 10%, v ih = +2.0v, v il = +0.8v, t a = t min to t max , unless otherwise noted. typical values are at v+ = +3v, t a = +25 c.) (notes 3, 4) parameter symbol conditions t a min typ max units dynamic characteristics +25 c 70 150 turn-on time t on v no_ or v nc_ = +1.5v, r l = 300 ? , c l = 35pf, figure 2 t min to t max 170 ns +25 c 30 60 turn-off time t off v no_ or v nc_ = +1.5v, r l = 300 ? , c l = 35pf, figure 2 t min to t max 70 ns +25 c 40 break-before-make (max4733 only, note 8) t bbm v no_ or v nc_ = +1.5v, r l = 300 ? , c l = 35pf, figure 3 t min to t max 1 ns charge injection q v gen = 0v, r gen = 0, c l = 1.0nf, figure 4 +25 c 7.5 pc on-channel -3db bandwidth bw signal = 0dbm, 50 ? in and out +25 c 300 mhz off-isolation (note 9) v iso f = 1mhz, v com_ = 1v rms , r l = 50 ? , c l = 5pf, figure 5 +25 c -72 db crosstalk (note 10) v ct f = 1mhz, v com_ = 1v rms , r l = 50 ? , c l = 5pf, figure 6 +25 c -108 db no_ or nc_ off-capacitance c off f = 1mhz, figure 7 +25 c 20 pf com_ off-capacitance c com_ ( off ) f = 1mhz, figure 7 +25 c 20 pf com_ on-capacitance c com_ ( on ) f = 1mhz, figure 7 +25 c 40 pf logic input input logic high v ih 1.4 v input logic low v il 0.8 v input leakage current i in v in_ = 0v or v+ -1 +0.005 +1 a supply power-supply range v+ 2.0 11 v positive supply current i+ v+ = +5.5v, v in_ = 0v or v+, all switches on or off 0.0001 1a
max4731/max4732/max4733 50 ?, dual spst analog switches in ucsp 4 _______________________________________________________________________________________ electrical characteristics single +5v supply (v+ = +5v 10%, v ih = +2.0v, v il = +0.8v, t a = t min to t max , unless otherwise noted. typical values are at v+ = +5v, t a = +25 c.) (notes 3, 4) parameter symbol conditions t a min typ max units analog switch analog signal range v com_ , v no_ , v nc_ 0v+v +25 c 8.5 25 on-resistance r on v+ = +4.5v, i com_ = 5ma, v no_ or v nc_ = +3.5v t min to t max 30 ? c 0.2 3 on-resistance matching between channels (notes 5, 6) ? r on v+ = +4.5v, i com_ = 5ma, v no_ or v nc_ = +3.5v t min to t max 4 ? c 25 on-resistance flatness (note 7) r flat ( on ) v+ = +4.5v, i com_ = 5ma, v no_ or v nc_ = +1v, +2v, +3v t min to t max 7 ? c -0.1 +0.1 no_ or nc_ off-leakage current (note 8) i no_ ( off ) i nc_ ( off ) v+ = +5.5v, v com_ = +1v, +4.5v; v no_ or v nc_ = +4.5v, +1v t min to t max -2 +2 na +25 c -0.1 +0.1 com_ off-leakage current (note 8) i com_ ( off ) v+ = +5.5v, v com_ = +1v, +4.5v; v no_ or v nc_ = +4.5v, +1v t min to t max -2 +2 na +25 c -0.2 +0.2 com_ on-leakage current (note 8) i com_ ( on ) v+ = +5.5v, v com_ = +1v, +4.5v; v no_ or v nc_ = +1v, +4.5v, or floating t min to t max -4 +4 na dynamic characteristics +25 c 47 85 turn-on time t on v no_ or v nc_ = +3.0v, r l = 300 ? , c l = 35pf, figure 2 t min to t max 95 ns +25 c 23 45 turn-off time t off v no_ or v nc_ = +3.0v, r l = 300 ? , c l = 35pf, figure 2 t min to t max 55 ns +25 c 25 break-before-make (max4733 only, note 8) t bbm v no_ or v nc_ = +3.0v, r l = 300 ? , c l = 35pf, figure 3 t min to t max 1 ns charge injection q v gen = 0v, r gen = 0, c l = 1.0nf, figure 4 +25 c 7.5 pc on-channel bandwidth bw signal = 0dbm, 50 ? in and out +25 c 300 mhz off-isolation (note 9) v iso f = 1mhz, v com_ = 1v rms , r l = 50 ? , c l = 5pf, figure 5 +25 c -72 db
max4731/max4732/max4733 50 ?, dual spst analog switches in ucsp _______________________________________________________________________________________ 5 note 3: the algebraic convention, where the most negative value is a minimum and the most positive value a maximum, is used in this data sheet. note 4: ucsp and tdfn parts are 100% tested at +25 c only, and guaranteed by design over temperature. max parts are 100% tested at +85 c and +25 c and guaranteed by design over temperature. note 5: ? r on = r on(max) - r on(min) . note 6: ucsp on-resistance matching between channels and on-resistance flatness guaranteed by design. note 7: flatness is defined as the difference between the maximum and minimum value of on-resistance as measured over the specified analog signal range. note 8: guaranteed by design. note 9: off-isolation = 20 log 10 (v no_ /v com_ ), v no_ = output, v com_ = input to off switch. note 10: between any two switches. electrical characteristics single +5v supply (v+ = +5v 10%, v ih = +2.0v, v il = +0.8v, t a = t min to t max , unless otherwise noted. typical values are at v+ = +5v, t a = +25 c.) (notes 3, 4) parameter symbol conditions t a min typ max units crosstalk (note 10) v ct f = 1mhz, v com_ = 1v rms , r l = 50 ? , c l = 5pf, figure 6 +25 c -108 db no_ or nc_ off-capacitance c off f = 1mhz, figure 7 +25 c 20 pf com_ off-capacitance c com_ ( off ) f = 1mhz, figure 7 +25 c 20 pf com_ on-capacitance c com_ ( on ) f = 1mhz, figure 7 +25 c 40 pf logic input input logic high v ih 2.0 v input logic low v il 0.8 v input leakage current i in v in_ = 0v or v+ -1 +0.005 +1 a supply power-supply range v+ 2.0 11 v positive supply current i+ v+ = +5.5v, v in_ = 0v or v+, all switches on or off 0.0001 1a
max4731/max4732/max4733 50 ?, dual spst analog switches in ucsp 6 _______________________________________________________________________________________ typical operating characteristics (t a = +25 c, unless otherwise noted.) on-resistance vs. v com max4731-33 toc01 v com (v) r on ( ? ) 8 6 4 2 10 20 30 40 50 0 010 v+ = +2.0v v+ = +3.0v v+ = +5.0v v+ = +10.0v on-resistance vs. v com (v+ = +2.5v) max4731-33 toc02 v com (v) r on ( ? ) 2.0 1.5 1.0 0.5 10 15 20 25 30 5 0 2.5 t a = +85 c t a = -40 c t a = +25 c on-resistance vs. v com (v+ = +3.0v) max4731-33 toc03 v com (v) r on ( ? ) 2.0 1.5 1.0 0.5 10 15 20 25 30 0 5 03.0 2.5 t a = +85 c t a = -40 c t a = +25 c on-resistance vs. v com (v+ = +5.0v) max4731-33 toc04 v com (v) r on ( ? ) 4 3 2 1 4 8 12 16 20 0 05 t a = +85 c t a = -40 c t a = +25 c on/off-leakage current vs. temperature maxz4731-33 toc05 temperature ( c) on/off-leakage current (pa) 60 40 20 0 -20 1 10 100 1000 0 -40 80 v+ = +5v on-leakage off-leakage charge injection vs. v com max4731-33 toc06 v com (v) charge injection (pc) 4 3 2 1 5 10 15 20 25 30 35 40 45 0 05 v+ = +5.0v v+ = +3.0v supply current vs. temperature max4731-33 toc07 temperature ( c) supply current (na) 80 60 -20 0 20 40 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 0 -40 v+ = +5v, +3v logic threshold voltage vs. supply voltage max4731-33 toc08 v+ (v) logic threshold voltage (v) 10 8 6 4 0.5 1.0 1.5 2.0 2.5 3.0 0 2 v in rising or falling turn-on/off time vs. supply voltage max4731-33 toc09 v+ (v) t on/off (ns) 8 6 4 20 40 60 80 100 120 0 210 t on t off
applications information operating considerations for high-voltage supply the max4731/max4732/max4733 operate to +11v with some precautions. the absolute maximum rating for v+ is +12v (referenced to gnd). when operating near this region, bypass v+ with a minimum 0.1f capacitor to ground as close to the ic as possible. logic levels the max4731/max4732/max4733 are ttl compatible when powered from a single +5v supply. when pow- ered from other supply voltages, the logic inputs should be driven rail-to-rail. for example, with a +11v supply, in1 and in2 should be driven low to 0v and high to 11v. with a +3.3v supply, in1 and in2 should be dri- ven low to 0v and high to 3.3v. driving in1 and in2 rail- to-rail minimizes power consumption. max4731/max4732/max4733 50 ?, dual spst analog switches in ucsp _______________________________________________________________________________________ 7 pin description typical operating characteristics (continued) (t a = +25 c, unless otherwise noted.) turn-on/off time vs. temperature max4731-33 toc10 temperature ( c) t on/off (ns) 60 40 -20 0 20 10 20 30 40 50 60 70 80 0 -40 80 t on , v+ = +3.0v t on , v+ = +5.0v t off , v+ = +3.0v t off , v+ = +5.0v frequency response max4731-33 toc11 frequency (hz) loss (db) 100m 10m 1m 100k -100 -80 -60 -40 -20 0 -120 10k 1g on-loss v+ = +3v off-isolation crosstalk total harmonic distortion vs. frequency max4731-33 toc12 frequency (hz) thd (%) 10k 1k 100 0.001 0.01 0.1 1 0.0001 10 100k v com = 2v p-p bw = 30khz r l = 1k ? v+ = +3.0v r l = 1k ? v+ = +5.0v r l = 100k ? v+ = +3.0v r l = 100k ? v+ = +5.0v pin max4731 max4732 max4733 ucsp max/ tdfn ucsp max/ tdfn ucsp max/ tdfn name function a1 1 a1 1 no1 analog-switch normally open terminal a2 2 a2 2 a2 2 com1 analog-switch common terminal a3 4 a3 4 a3 4 gnd ground. connect to digital ground. b1 7 b1 7 b1 7 in1 logic-control digital input b3 3 b3 3 b3 3 in2 logic-control digital input c1 8 c1 8 c1 8 v+ positive supply voltage input c2 6 c2 6 c2 6 com2 analog-switch common terminal c3 5 no2 analog-switch normally open terminal a1 1 nc1 analog-switch normally closed terminal c3 5 c3 5 nc2 analog-switch normally closed terminal ep (tdfn onl y) ep (tdfn onl y) ep (tdfn onl y) ep exposed pad. connect to v+.
max4731/max4732/max4733 analog signal levels analog signals that range over the entire supply voltage (gnd to v+) pass with very little change in r on (see typical operating characteristics ). the bidirectional switches allow no_, nc_, and com_ connections to be used as either inputs or outputs. power-supply sequencing and overvoltage protection caution: do not exceed the absolute maximum ratings. stresses beyond the listed ratings can cause permanent damage to the devices. proper power-supply sequencing is recommended for all cmos devices. always apply v+ before applying analog signals, especially if the analog signal is not current limited. if this sequencing is not possible, and if the analog inputs are not current limited to < 20ma, add a small-signal diode, d1, as shown in figure 1. if the analog signal can dip below gnd, add d2. adding protection diodes reduces the analog signal range to a diode drop (about 0.7v) below v+ (for d1), and to a diode drop above ground (for d2). leakage is unaffect- ed by adding the diodes. on-resistance increases slightly at low supply voltages. maximum supply volt- age (v+) must not exceed +11v. adding protection diodes causes the logic thresholds to be shifted relative to the power-supply rails. the most significant shift occurs when using low supply voltages (+5v or less). with a +5v supply, ttl compatibility is not guaranteed when protection diodes are added. driving in1 and in2 all the way to the supply rails (i.e., to a diode drop higher than the v+ pin, or to a diode drop lower than the gnd pin) is always acceptable. protection diodes d1 and d2 also protect against some overvoltage situations. using the circuit in figure 1, no damage results if the supply voltage is below the absolute maximum rating (+12v) and if a fault voltage up to the absolute maximum rating (v+ + 0.3v) is applied to an analog signal terminal. ucsp applications information for the latest application details on uscp construction, dimensions, tape carrier information, printed circuit board techniques, bump-pad layout, and recommend- ed reflow temperature profile as well as the latest infor- mation on reliability testing results, go to the maxim web site at www.maxim-ic.com/ucsp to find the application note: ucsp? wafer-level chip-scale package . 50 ?, dual spst analog switches in ucsp 8 _______________________________________________________________________________________ max4731 max4732 max4733 no_ com_ gnd v+ *internal protection diodes. d2 d1 external blocking diode external blocking diode gnd v+ * * * * figure 1. overvoltage protection using external blocking diodes test circuits/timing diagrams
max4731/max4732/max4733 50 ?, dual spst analog switches in ucsp _______________________________________________________________________________________ 9 test circuits/timing diagrams (continued) 50% v il logic input r l 300 ? in_ c l includes fixture and stray capacitance. ( r l ) v n_ v ih t off 0v no_ or nc_ 0.9 x v out 0.9 x v out t on v out switch output logic input logic input waveforms inverted for switches that have the opposite logic sense. v+ com_ c l 35pf v+ v out max4731 max4732 max4733 gnd r l + r on t r < 5ns t f < 5ns v out = v n_ figure 2. switching time 50% 0.9 x v 0ut1 v+ 0v 0v logic input switch output 2 (v out2 ) 0v 0.9 x v out2 t bbm t bbm logic input r l2 300 ? gnd c l includes fixture and stray capacitance. nc2 in2 in1 no1 v out2 v+ v+ c l2 35pf v n_ r l1 300 ? v out1 c l1 35pf com1 com2 switch output 1 (v out1 ) max4733 t r < 5ns t f < 5ns figure 3. break-before-make interval (max4733 only) v gen gnd com c l 1nf v out v+ v out in off on off ? v out q = ( ? v out )(c l ) nc_ or no_ in depends on switch configuration; input polarity determined by sense of switch. off on off in v il to v ih v+ r gen in_ max4731 max4732 max4733 figure 4. charge injection
max4731/max4732/max4733 50 ?, dual spst analog switches in ucsp 10 ______________________________________________________________________________________ in_ v il or v ih signal generator 0dbm v+ 10nf analyzer nc_ or no_ r l gnd com_ v+ max4731 max4732 max4733 v- note: dual supplies used to accomodate ground-referenced instruments. 10nf figure 5. off-isolation/on-channel bandwidth signal generator 0dbm v+ 10nf analyzer no2/nc2 r l com1 0 or 2.4v in1 no1/nc1 50 ? com2 in2 0 or 2.4v n.c. v+ max4731 max4732 max4733 gnd v- note: dual supplies used to accomodate ground-referenced instruments. 10nf figure 6. crosstalk capacitance meter nc_ or no_ com_ gnd in_ v il or v ih 10nf v+ f = 1mhz v+ max4731 max4732 max4733 figure 7. channel off/on-capacitance chip information transitor count: 68 process: cmos test circuits/timing diagrams (continued)
max4731/max4732/max4733 50 ?, dual spst analog switches in ucsp ______________________________________________________________________________________ 11 top view max 8 7 6 5 1 2 3 4 v+ in1 com2 no2 gnd in2 com1 no1 max4731 max4733 max 8 7 6 5 1 2 3 4 v+ in1 com2 nc2 gnd in2 com1 no1 max 8 7 6 5 1 2 3 4 v+ in1 com2 nc2 gnd in2 com1 nc1 max4732 max4733 nc2 v+ gnd in2 in1 no1 com1 com2 a1 b1 c1 c2 c3 b3 a3 a2 in_ 0 1 no1 max4733 on off switches shown for logic "0" input nc2 off on com1 gnd no1 tdfn max4733 com2 nc2 in1 1 2 in2 3 4 8 7 6 5 ucsp top view (bumps on bottom) v+ ep ep = exposed pad pin configurations/functional diagrams/truth tables (continued)
max4731/max4732/max4733 50 ?, dual spst analog switches in ucsp 12 ______________________________________________________________________________________ package information (the package drawing(s) in this data sheet may not reflect the most current specifications. for the latest package outline info rmation go to www.maxim-ic.com/packages .) 9lucsp, 3x3.eps package outline, 3x3 ucsp 21-0093 1 1 k
max4731/max4732/max4733 50 ?, dual spst analog switches in ucsp ______________________________________________________________________________________ 13 6, 8, &10l, dfn thin.eps h 1 2 21-0137 package outline, 6,8,10 & 14l, tdfn, exposed pad, 3x3x0.80 mm common dimensions symbol min. max. a 0.70 0.80 d 2.90 3.10 e 2.90 3.10 a1 0.00 0.05 l 0.20 0.40 pkg. code n d2 e2 e jedec spec b [(n/2)-1] x e package variations 0.25 min. k a2 0.20 ref. 2.30?0.10 1.50?0.10 6 t633-1 0.95 bsc m o229 / weea 1.90 ref 0.40?0.05 1.95 ref 0.30?0.05 0.65 bsc 2.30?0.10 8 t833-1 2.00 ref 0.25?0.05 0.50 bsc 2.30?0.10 10 t1033-1 2.40 ref 0.20?0.05 - - - - 0.40 bsc 1.70?0.10 2.30?0.10 14 t1433-1 1.50?0.10 1.50?0.10 mo229 / weec mo229 / weed-3 0.40 bsc - - - - 0.20?0.05 2.40 ref t1433-2 14 2.30?0.10 1.70?0.10 t633-2 6 1.50?0.10 2.30?0.10 0.95 bsc m o229 / weea 0.40?0.05 1.90 ref t833-2 8 1.50?0.10 2.30?0.10 0.65 bsc m o229 / weec 0.30?0.05 1.95 ref t833-3 8 1.50?0.10 2.30?0.10 0.65 bsc m o229 / weec 0.30?0.05 1.95 ref -drawing not to scale- h 2 2 21-0137 package outline, 6,8,10 & 14l, tdfn, exposed pad, 3x3x0.80 mm 2.30?0.10 mo229 / weed-3 2.00 ref 0.25?0.05 0.50 bsc 1.50?0.10 10 t1033-2 package information (continued) (the package drawing(s) in this data sheet may not reflect the most current specifications. for the latest package outline info rmation go to www.maxim-ic.com/packages .)
package information (continued) (the package drawing(s) in this data sheet may not reflect the most current specifications. for the latest package outline info rmation go to www.maxim-ic.com/packages .) max4731/max4732/max4733 50 ?, dual spst analog switches in ucsp maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circu it patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. 14 ____________________maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 ? 2006 maxim integrated products is a registered trademark of maxim integrated products, inc. 8lumaxd.eps package outline, 8l umax/usop 1 1 21-0036 j rev. document control no. approval proprietary information title: max 0.043 0.006 0.014 0.120 0.120 0.198 0.026 0.007 0.037 0.0207 bsc 0.0256 bsc a2 a1 c e b a l front view side view e h 0.6 ? 0.1 0.6 ? 0.1 ?.50?.1 1 top view d 8 a2 0.030 bottom view 1 6 s b l h e d e c 0 0.010 0.116 0.116 0.188 0.016 0.005 8 4x s inches - a1 a min 0.002 0.95 0.75 0.5250 bsc 0.25 0.36 2.95 3.05 2.95 3.05 4.78 0.41 0.65 bsc 5.03 0.66 6 0 0.13 0.18 max min millimeters - 1.10 0.05 0.15 dim revision history pages changed at rev 2: 1, 2, 7, 8, 11, 14

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